Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.


software_version_and_target_device
betaFALSE build_version2288692
date_generatedWed Aug 28 11:48:10 2019 os_platformWIN64
product_versionVivado v2018.2.1 (64-bit) project_id0651c353d5fc43da95ff47d82f929afc
project_iteration1 random_ida65ca56b68665a9a979d59e8404b2729
registration_id176233316_1777497009_210621211_364 route_designTRUE
target_devicexc7a35ti target_familyartix7
target_packagecsg324 target_speed-1L
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-6700 CPU @ 3.40GHz cpu_speed3408 MHz
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
system_ram17.000 GB total_processors1

vivado_usage
gui_handlers
applyrsbmultiautomationdialog_checkbox_tree=2 basedialog_ok=9 boardchooser_board_table=1 boardtreepanel_board_tree_panel=8
coretreetablepanel_core_tree_table=3 filesetpanel_file_set_panel_tree=2 flownavigatortreepanel_flow_navigator_tree=2 gettingstartedview_create_new_project=1
pacommandnames_create_top_hdl=1 pacommandnames_regenerate_layout=4 pacommandnames_validate_rsb_design=1 projectnamechooser_project_name=1
rsbapplyautomationbar_run_block_automation=1 rsbapplyautomationbar_run_connection_automation=2 systembuilderview_add_ip=1
java_command_handlers
autoconnectboardcomp=5 createblockdesign=1 createtophdl=1 customizersbblock=3
editdelete=2 newproject=1 regeneratersblayout=4 runbitgen=1
validatersbdesign=1
other_data
guimode=1
project_data
constraintsetcount=0 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=3 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=17 totalsynthesisruns=17

unisim_transformation
post_unisim_transformation
and2b1l=4 bscane2=1 bufg=7 bufh=1
carry4=174 fdce=246 fdpe=80 fdre=12376
fdse=474 gnd=595 ibuf=19 ibuf_intermdisable=16
ibufds_intermdisable_int=4 idelayctrl=1 idelaye2=16 in_fifo=2
inv=3 iserdese2=16 lut1=566 lut2=1224
lut3=2848 lut4=1824 lut5=2596 lut6=2780
mmcme2_adv=2 muxf7=114 obuf=25 obufds=2
obuft=30 obuftds=4 oddr=5 oserdese2=43
out_fifo=4 phaser_in_phy=2 phaser_out_phy=4 phaser_ref=1
phy_control=1 plle2_adv=1 ramb36e1=18 ramd32=2718
rams32=858 srl16e=216 srlc16e=8 srlc32e=347
vcc=530 xadc=1
pre_unisim_transformation
and2b1l=4 bscane2=1 bufg=7 bufh=1
carry4=174 fdce=246 fdpe=80 fdre=12376
fdse=474 gnd=595 ibuf=7 idelayctrl=1
idelaye2=16 in_fifo=2 iobuf=12 iobuf_intermdisable=16
iobufds_intermdisable=2 iserdese2=16 lut1=566 lut2=1224
lut3=2848 lut4=1824 lut5=2532 lut6=2716
lut6_2=64 mmcme2_adv=2 muxf7=114 obuf=25
obufds=1 obuft=2 oddr=5 oserdese2=43
out_fifo=4 phaser_in_phy=2 phaser_out_phy=4 phaser_ref=1
phy_control=1 plle2_adv=1 ram32m=429 ram32x1d=72
ramb36e1=18 srl16e=216 srlc16e=8 srlc32e=347
vcc=530 xadc=1

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=8 bram_ports_total=36 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=10835 srls_augmented=0
srls_newly_gated=0 srls_total=488

ip_statistics
IP_Integrator/1
bdsource=SBD core_container=NA iptotal=1 maxhierdepth=1
numblks=37 numhdlrefblks=0 numhierblks=8 numhlsblks=0
numnonxlnxblks=0 numpkgbdblks=0 numreposblks=29 numsysgenblks=0
synth_mode=Global x_iplanguage=VERILOG x_iplibrary=BlockDiagram x_ipname=bd_afc3
x_ipvendor=xilinx.com x_ipversion=1.00.a
IP_Integrator/2
bdsource=USER core_container=NA da_axi4_cnt=3 da_board_cnt=2
da_mb_cnt=1 iptotal=1 maxhierdepth=1 numblks=22
numhdlrefblks=0 numhierblks=6 numhlsblks=0 numnonxlnxblks=0
numpkgbdblks=0 numreposblks=16 numsysgenblks=0 synth_mode=OOC_per_IP
x_iplanguage=VERILOG x_iplibrary=BlockDiagram x_ipname=design_1 x_ipvendor=xilinx.com
x_ipversion=1.00.a
MDM/1
c_avoid_primitives=0 c_bscanid=76547328 c_data_size=32 c_dbg_mem_access=0
c_dbg_reg_access=0 c_debug_interface=0 c_ext_trig_reset_value=0xF1234 c_family=artix7
c_interconnect=2 c_jtag_chain=2 c_m_axi_addr_width=32 c_m_axi_data_width=32
c_m_axi_thread_id_width=1 c_m_axis_data_width=32 c_m_axis_id_width=7 c_mb_dbg_ports=1
c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=4 c_s_axi_data_width=32 c_trace_async_reset=0
c_trace_clk_freq_hz=200000000 c_trace_clk_out_phase=90 c_trace_data_width=32 c_trace_id=110
c_trace_output=0 c_trace_protocol=1 c_use_bscan=0 c_use_config_reset=0
c_use_cross_trigger=0 c_use_uart=0 core_container=NA iptotal=1
x_ipcorerevision=14 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=mdm
x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=3.2
MicroBlaze/1
c_addr_tag_bits=14 c_allow_dcache_wr=1 c_allow_icache_wr=1 c_area_optimized=0
c_async_interrupt=1 c_async_wakeup=3 c_avoid_primitives=0 c_base_vectors=0x0000000000000000
c_branch_target_cache_size=0 c_cache_byte_size=16384 c_d_axi=1 c_d_lmb=1
c_daddr_size=32 c_data_size=32 c_dcache_addr_tag=14 c_dcache_always_used=1
c_dcache_baseaddr=0x0000000080000000 c_dcache_byte_size=16384 c_dcache_data_width=0 c_dcache_force_tag_lutram=0
c_dcache_highaddr=0x000000008fffffff c_dcache_line_len=4 c_dcache_use_writeback=0 c_dcache_victims=0
c_debug_counter_width=32 c_debug_enabled=1 c_debug_event_counters=5 c_debug_external_trace=0
c_debug_interface=0 c_debug_latency_counters=1 c_debug_profile_size=0 c_debug_trace_async_reset=0
c_debug_trace_size=8192 c_div_zero_exception=0 c_dynamic_bus_sizing=0 c_ecc_use_ce_exception=0
c_edge_is_positive=1 c_endianness=1 c_family=artix7 c_fault_tolerant=0
c_fpu_exception=0 c_freq=83333333 c_fsl_exception=0 c_fsl_links=0
c_i_axi=0 c_i_lmb=1 c_iaddr_size=32 c_icache_always_used=1
c_icache_baseaddr=0x0000000080000000 c_icache_data_width=0 c_icache_force_tag_lutram=0 c_icache_highaddr=0x000000008fffffff
c_icache_line_len=4 c_icache_streams=0 c_icache_victims=0 c_ill_opcode_exception=0
c_imprecise_exceptions=0 c_instance=design_1_microblaze_0_0 c_instr_size=32 c_interconnect=2
c_interrupt_is_edge=0 c_lockstep_master=0 c_lockstep_slave=0 c_m0_axis_data_width=32
c_m10_axis_data_width=32 c_m11_axis_data_width=32 c_m12_axis_data_width=32 c_m13_axis_data_width=32
c_m14_axis_data_width=32 c_m15_axis_data_width=32 c_m1_axis_data_width=32 c_m2_axis_data_width=32
c_m3_axis_data_width=32 c_m4_axis_data_width=32 c_m5_axis_data_width=32 c_m6_axis_data_width=32
c_m7_axis_data_width=32 c_m8_axis_data_width=32 c_m9_axis_data_width=32 c_m_axi_d_bus_exception=0
c_m_axi_dc_addr_width=32 c_m_axi_dc_aruser_width=5 c_m_axi_dc_awuser_width=5 c_m_axi_dc_buser_width=1
c_m_axi_dc_data_width=32 c_m_axi_dc_exclusive_access=0 c_m_axi_dc_ruser_width=1 c_m_axi_dc_thread_id_width=1
c_m_axi_dc_user_value=31 c_m_axi_dc_wuser_width=1 c_m_axi_dp_addr_width=32 c_m_axi_dp_data_width=32
c_m_axi_dp_exclusive_access=0 c_m_axi_dp_thread_id_width=1 c_m_axi_i_bus_exception=0 c_m_axi_ic_addr_width=32
c_m_axi_ic_aruser_width=5 c_m_axi_ic_awuser_width=5 c_m_axi_ic_buser_width=1 c_m_axi_ic_data_width=32
c_m_axi_ic_ruser_width=1 c_m_axi_ic_thread_id_width=1 c_m_axi_ic_user_value=31 c_m_axi_ic_wuser_width=1
c_m_axi_ip_addr_width=32 c_m_axi_ip_data_width=32 c_m_axi_ip_thread_id_width=1 c_mmu_dtlb_size=4
c_mmu_itlb_size=2 c_mmu_privileged_instr=0 c_mmu_tlb_access=3 c_mmu_zones=16
c_num_sync_ff_clk=2 c_num_sync_ff_clk_debug=2 c_num_sync_ff_clk_irq=1 c_num_sync_ff_dbg_clk=1
c_num_sync_ff_dbg_trace_clk=2 c_number_of_pc_brk=1 c_number_of_rd_addr_brk=0 c_number_of_wr_addr_brk=0
c_opcode_0x0_illegal=0 c_optimization=0 c_pc_width=32 c_piaddr_size=32
c_pvr=0 c_pvr_user1=0x00 c_pvr_user2=0x00000000 c_reset_msr=0x00000000
c_s0_axis_data_width=32 c_s10_axis_data_width=32 c_s11_axis_data_width=32 c_s12_axis_data_width=32
c_s13_axis_data_width=32 c_s14_axis_data_width=32 c_s15_axis_data_width=32 c_s1_axis_data_width=32
c_s2_axis_data_width=32 c_s3_axis_data_width=32 c_s4_axis_data_width=32 c_s5_axis_data_width=32
c_s6_axis_data_width=32 c_s7_axis_data_width=32 c_s8_axis_data_width=32 c_s9_axis_data_width=32
c_sco=0 c_unaligned_exceptions=0 c_use_barrel=0 c_use_branch_target_cache=0
c_use_config_reset=0 c_use_dcache=1 c_use_div=0 c_use_ext_brk=0
c_use_ext_nm_brk=0 c_use_extended_fsl_instr=0 c_use_fpu=0 c_use_hw_mul=0
c_use_icache=1 c_use_interrupt=2 c_use_mmu=0 c_use_msr_instr=0
c_use_non_secure=0 c_use_pcmp_instr=0 c_use_reorder_instr=1 c_use_stack_protection=0
core_container=NA iptotal=1 x_ipcorerevision=7 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=microblaze x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=10.0
axi_crossbar_v2_1_18_axi_crossbar/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=2 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=0 c_family=artix7
c_m_axi_addr_width=0x000000100000001000000010 c_m_axi_base_addr=0x000000004060000000000000400000000000000041200000 c_m_axi_read_connectivity=0x000000010000000100000001 c_m_axi_read_issuing=0x000000010000000100000001
c_m_axi_secure=0x000000000000000000000000 c_m_axi_write_connectivity=0x000000010000000100000001 c_m_axi_write_issuing=0x000000010000000100000001 c_num_addr_ranges=1
c_num_master_slots=3 c_num_slave_slots=1 c_r_register=1 c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 c_s_axi_read_acceptance=0x00000001 c_s_axi_single_thread=0x00000001 c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 core_container=NA iptotal=1 x_ipcorerevision=18
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2018.2.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_gpio/1
c_all_inputs=1 c_all_inputs_2=0 c_all_outputs=0 c_all_outputs_2=0
c_dout_default=0x00000000 c_dout_default_2=0x00000000 c_family=artix7 c_gpio2_width=12
c_gpio_width=4 c_interrupt_present=1 c_is_dual=1 c_s_axi_addr_width=9
c_s_axi_data_width=32 c_tri_default=0xFFFFFFFF c_tri_default_2=0xFFFFFFFF core_container=NA
iptotal=1 x_ipcorerevision=19 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=axi_gpio x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=2.0
axi_intc/1
c_async_intr=0xFFFFFFFE c_cascade_master=0 c_disable_synchronizers=0 c_en_cascade_mode=0
c_enable_async=0 c_family=artix7 c_has_cie=1 c_has_fast=1
c_has_ilr=0 c_has_ipr=1 c_has_ivr=1 c_has_sie=1
c_instance=design_1_microblaze_0_axi_intc_0 c_irq_active=0x1 c_irq_is_level=1 c_ivar_reset_value=0x00000010
c_kind_of_edge=0xFFFFFFFF c_kind_of_intr=0xfffffffe c_kind_of_lvl=0xFFFFFFFF c_mb_clk_not_connected=1
c_num_intr_inputs=1 c_num_sw_intr=0 c_num_sync_ff=2 c_s_axi_addr_width=9
c_s_axi_data_width=32 core_container=NA iptotal=1 x_ipcorerevision=11
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_intc x_ipproduct=Vivado 2018.2.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=4.1
axi_uartlite/1
c_baudrate=9600 c_data_bits=8 c_family=artix7 c_odd_parity=0
c_s_axi_aclk_freq_hz=83333333 c_s_axi_addr_width=4 c_s_axi_data_width=32 c_use_parity=0
core_container=NA iptotal=1 x_ipcorerevision=21 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_uartlite x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.0
bd_afc3/1
advanced_properties=0 component_name=design_1_axi_smc_0 core_container=NA has_aresetn=1
iptotal=1 num_clks=1 num_mi=1 num_si=2
x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=smartconnect
x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
blk_mem_gen_v8_4_1/1
c_addra_width=32 c_addrb_width=32 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=8 c_common_clk=0
c_count_18k_bram=0 c_count_36k_bram=8 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=1
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=1 c_est_power_summary=Estimated Power for IP _ 19.3686 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=1 c_has_enb=1
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=1
c_has_rstb=1 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=design_1_lmb_bram_0.mem
c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=0 c_mem_type=2 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=8192 c_read_depth_b=8192 c_read_width_a=32 c_read_width_b=32
c_rst_priority_a=CE c_rst_priority_b=CE c_rstram_a=0 c_rstram_b=0
c_sim_collision_check=ALL c_use_bram_block=1 c_use_byte_wea=1 c_use_byte_web=1
c_use_default_data=0 c_use_ecc=0 c_use_softecc=0 c_use_uram=0
c_wea_width=4 c_web_width=4 c_write_depth_a=8192 c_write_depth_b=8192
c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST c_write_width_a=32 c_write_width_b=32
c_xdevicefamily=artix7 core_container=false iptotal=1 x_ipcorerevision=1
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=blk_mem_gen x_ipproduct=Vivado 2018.2.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=8.4
clk_wiz_v6_0_1_0_0/1
clkin1_period=10.000 clkin2_period=10.000 clock_mgr_type=NA component_name=design_1_clk_wiz_0_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=2 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
lmb_bram_if_cntlr/1
c_baseaddr=0x0000000000000000 c_bram_awidth=32 c_ce_counter_width=0 c_ce_failing_registers=0
c_ecc=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ecc_status_registers=0
c_family=artix7 c_fault_inject=0 c_highaddr=0x0000000000007FFF c_interconnect=0
c_lmb_awidth=32 c_lmb_dwidth=32 c_mask=0x00000000c0000000 c_mask1=0x0000000000800000
c_mask2=0x0000000000800000 c_mask3=0x0000000000800000 c_num_lmb=1 c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 c_ue_failing_registers=0 c_write_access=2 core_container=NA
iptotal=1 x_ipcorerevision=15 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=4.0
lmb_bram_if_cntlr/2
c_baseaddr=0x0000000000000000 c_bram_awidth=32 c_ce_counter_width=0 c_ce_failing_registers=0
c_ecc=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ecc_status_registers=0
c_family=artix7 c_fault_inject=0 c_highaddr=0x0000000000007FFF c_interconnect=0
c_lmb_awidth=32 c_lmb_dwidth=32 c_mask=0x0000000080000000 c_mask1=0x0000000000800000
c_mask2=0x0000000000800000 c_mask3=0x0000000000800000 c_num_lmb=1 c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 c_ue_failing_registers=0 c_write_access=2 core_container=NA
iptotal=1 x_ipcorerevision=15 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=4.0
lmb_v10/1
c_ext_reset_high=1 c_lmb_awidth=32 c_lmb_dwidth=32 c_lmb_num_slaves=1
core_container=NA iptotal=2 x_ipcorerevision=9 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=lmb_v10 x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=3.0
mig_7series_v4_1/1
axi_enable=1 burst_mode=8 burst_type=SEQ ca_mirror=OFF
clk_period=3000 clkin_period=6000 core_container=NA data_mask=1
debug_port=OFF dq_width=16 ecc=OFF interface_type=DDR3
internal_vref=1 iptotal=1 language=Verilog level=CONTROLLER
memory_address_map=BANK_ROW_COLUMN memory_part=mt41k128m16xx-15e memory_type=COMP no_of_controllers=1
ordering=NORM output_drv=LOW phy_ratio=4 refclk_freq=200
refclk_type=NO_BUFFER rtt_nom=40 synthesis_tool=Vivado sysclk_type=NO_BUFFER
use_cs_port=1 use_odt_port=1 vccaux_io=1.8V
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=1 c_ext_rst_width=4
c_family=artix7 c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=12
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2018.2.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
sc_exit_v1_0_7_top/1
c_addr_width=28 c_enable_pipelining=0x1 c_family=artix7 c_has_lock=0
c_is_cascaded=0 c_m_aruser_width=0 c_m_awuser_width=0 c_m_buser_width=0
c_m_id_width=0 c_m_limit_read_length=1 c_m_limit_write_length=1 c_m_protocol=0
c_m_ruser_bits_per_byte=0 c_m_ruser_width=0 c_m_wuser_bits_per_byte=0 c_m_wuser_width=0
c_max_ruser_bits_per_byte=0 c_max_wuser_bits_per_byte=0 c_mep_identifier_width=1 c_num_msc=1
c_rdata_width=128 c_read_acceptance=1 c_s_id_width=1 c_single_issuing=0
c_ssc_route_array=0b1001 c_ssc_route_width=2 c_wdata_width=128 c_write_acceptance=1
core_container=NA iptotal=1 x_ipcorerevision=7 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=sc_exit x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
sc_mmu_v1_0_6_top/1
c_addr_width=32 c_enable_pipelining=0x1 c_family=artix7 c_id_width=0
c_is_cascaded=0 c_msc_route_array=0b1 c_msc_route_width=1 c_num_msc=1
c_num_seg=1 c_rdata_width=32 c_read_acceptance=32 c_s_aruser_width=0
c_s_awuser_width=0 c_s_buser_width=0 c_s_protocol=0 c_s_ruser_width=0
c_s_wuser_width=0 c_seg_base_addr_array=0x0000000080000000 c_seg_secure_read_array=0b0 c_seg_secure_write_array=0b0
c_seg_sep_route_array=0x0000000000000000 c_seg_size_array=0x0000001c c_seg_supports_read_array=0x1 c_seg_supports_write_array=0x1
c_single_issuing=0 c_supports_read_decerr=1 c_supports_wrap=1 c_supports_write_decerr=1
c_wdata_width=32 c_write_acceptance=32 core_container=NA iptotal=1
x_ipcorerevision=6 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_mmu
x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_mmu_v1_0_6_top/2
c_addr_width=32 c_enable_pipelining=0x1 c_family=artix7 c_id_width=0
c_is_cascaded=0 c_msc_route_array=0b1 c_msc_route_width=1 c_num_msc=1
c_num_seg=1 c_rdata_width=32 c_read_acceptance=32 c_s_aruser_width=0
c_s_awuser_width=0 c_s_buser_width=0 c_s_protocol=0 c_s_ruser_width=0
c_s_wuser_width=0 c_seg_base_addr_array=0x0000000080000000 c_seg_secure_read_array=0b0 c_seg_secure_write_array=0b0
c_seg_sep_route_array=0x0000000000000000 c_seg_size_array=0x0000001c c_seg_supports_read_array=0x1 c_seg_supports_write_array=0x1
c_single_issuing=0 c_supports_read_decerr=1 c_supports_wrap=1 c_supports_write_decerr=1
c_wdata_width=32 c_write_acceptance=32 core_container=NA iptotal=1
x_ipcorerevision=6 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_mmu
x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_node_v1_0_9_top/10
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=0 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x0000000400000004 c_m_pipeline=0 c_m_send_pipeline=0
c_max_payld_bytes=16 c_num_mi=1 c_num_si=1 c_payld_width=148
c_s_latency=1 c_s_num_bytes_array=0x00000010 c_s_pipeline=0 c_sc_route_width=2
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=512 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/11
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=0 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x0000000400000004 c_m_pipeline=0 c_m_send_pipeline=0
c_max_payld_bytes=16 c_num_mi=1 c_num_si=1 c_payld_width=148
c_s_latency=1 c_s_num_bytes_array=0x00000010 c_s_pipeline=0 c_sc_route_width=2
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=512 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/12
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=1 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000010 c_m_pipeline=0 c_m_send_pipeline=1
c_max_payld_bytes=16 c_num_mi=1 c_num_si=1 c_payld_width=160
c_s_latency=0 c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=512 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/1
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=2 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000010 c_m_pipeline=0 c_m_send_pipeline=0
c_max_payld_bytes=16 c_num_mi=1 c_num_si=2 c_payld_width=138
c_s_latency=1 c_s_num_bytes_array=0x0000001000000010 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/2
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=3 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000010 c_m_pipeline=0 c_m_send_pipeline=0
c_max_payld_bytes=16 c_num_mi=1 c_num_si=2 c_payld_width=138
c_s_latency=1 c_s_num_bytes_array=0x0000001000000010 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/3
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=4 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x0000001000000010 c_m_pipeline=0 c_m_send_pipeline=1
c_max_payld_bytes=16 c_num_mi=2 c_num_si=1 c_payld_width=6
c_s_latency=0 c_s_num_bytes_array=0x00000010 c_s_pipeline=0 c_sc_route_width=2
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/4
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=0 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x0000001000000010 c_m_pipeline=0 c_m_send_pipeline=1
c_max_payld_bytes=16 c_num_mi=2 c_num_si=1 c_payld_width=148
c_s_latency=0 c_s_num_bytes_array=0x00000010 c_s_pipeline=0 c_sc_route_width=2
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/5
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=1 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000010 c_m_pipeline=0 c_m_send_pipeline=0
c_max_payld_bytes=16 c_num_mi=1 c_num_si=2 c_payld_width=160
c_s_latency=1 c_s_num_bytes_array=0x0000001000000010 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/6
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=2 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000010 c_m_pipeline=0 c_m_send_pipeline=1
c_max_payld_bytes=16 c_num_mi=1 c_num_si=1 c_payld_width=138
c_s_latency=0 c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/7
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=2 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000010 c_m_pipeline=0 c_m_send_pipeline=1
c_max_payld_bytes=16 c_num_mi=1 c_num_si=1 c_payld_width=138
c_s_latency=0 c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/8
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=3 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000010 c_m_pipeline=0 c_m_send_pipeline=1
c_max_payld_bytes=16 c_num_mi=1 c_num_si=1 c_payld_width=138
c_s_latency=0 c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/9
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=4 c_disable_ip=0 c_enable_pipelining=0x01 c_family=artix7
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x0000000400000004 c_m_pipeline=0 c_m_send_pipeline=0
c_max_payld_bytes=16 c_num_mi=1 c_num_si=1 c_payld_width=6
c_s_latency=1 c_s_num_bytes_array=0x00000010 c_s_pipeline=0 c_sc_route_width=2
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_si_converter_v1_0_6_top/1
c_addr_width=32 c_enable_pipelining=0x1 c_has_burst=1 c_id_width=1
c_is_cascaded=0 c_limit_read_length=0 c_limit_write_length=0 c_max_ruser_bits_per_byte=0
c_max_wuser_bits_per_byte=0 c_mep_identifier_width=1 c_msc_rdata_width_array=0x00000080 c_msc_wdata_width_array=0x00000080
c_num_msc=1 c_num_read_threads=1 c_num_seg=1 c_num_write_threads=1
c_rdata_width=32 c_read_acceptance=32 c_read_watermark=0 c_s_ruser_bits_per_byte=0
c_s_wuser_bits_per_byte=0 c_sep_protocol_array=0x00000000 c_sep_rdata_width_array=0x00000080 c_sep_wdata_width_array=0x00000080
c_single_issuing=0 c_supports_narrow=0 c_wdata_width=32 c_write_acceptance=32
c_write_watermark=0 core_container=NA iptotal=1 x_ipcorerevision=6
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_si_converter x_ipproduct=Vivado 2018.2.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_si_converter_v1_0_6_top/2
c_addr_width=32 c_enable_pipelining=0x1 c_has_burst=1 c_id_width=1
c_is_cascaded=0 c_limit_read_length=0 c_limit_write_length=0 c_max_ruser_bits_per_byte=0
c_max_wuser_bits_per_byte=0 c_mep_identifier_width=1 c_msc_rdata_width_array=0x00000080 c_msc_wdata_width_array=0x00000080
c_num_msc=1 c_num_read_threads=1 c_num_seg=1 c_num_write_threads=1
c_rdata_width=32 c_read_acceptance=32 c_read_watermark=0 c_s_ruser_bits_per_byte=0
c_s_wuser_bits_per_byte=0 c_sep_protocol_array=0x00000000 c_sep_rdata_width_array=0x00000080 c_sep_wdata_width_array=0x00000080
c_single_issuing=0 c_supports_narrow=0 c_wdata_width=32 c_write_acceptance=32
c_write_watermark=0 core_container=NA iptotal=1 x_ipcorerevision=6
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_si_converter x_ipproduct=Vivado 2018.2.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_switchboard_v1_0_5_top/1
c_connectivity=11 c_m_pipelines=1 c_num_mi=1 c_num_si=2
c_payld_width=138 c_s_latency=0 c_s_pipelines=0 c_testing_mode=0
core_container=NA iptotal=1 k_max_info_width=1 x_ipcorerevision=5
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_switchboard x_ipproduct=Vivado 2018.2.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_switchboard_v1_0_5_top/2
c_connectivity=11 c_m_pipelines=1 c_num_mi=1 c_num_si=2
c_payld_width=138 c_s_latency=0 c_s_pipelines=0 c_testing_mode=0
core_container=NA iptotal=1 k_max_info_width=1 x_ipcorerevision=5
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_switchboard x_ipproduct=Vivado 2018.2.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_switchboard_v1_0_5_top/3
c_connectivity=0b11 c_m_pipelines=1 c_num_mi=2 c_num_si=1
c_payld_width=148 c_s_latency=0 c_s_pipelines=0 c_testing_mode=0
core_container=NA iptotal=1 k_max_info_width=1 x_ipcorerevision=5
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_switchboard x_ipproduct=Vivado 2018.2.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_switchboard_v1_0_5_top/4
c_connectivity=11 c_m_pipelines=1 c_num_mi=1 c_num_si=2
c_payld_width=160 c_s_latency=0 c_s_pipelines=0 c_testing_mode=0
core_container=NA iptotal=1 k_max_info_width=1 x_ipcorerevision=5
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_switchboard x_ipproduct=Vivado 2018.2.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
xlconcat_v2_1_1_xlconcat/1
core_container=NA dout_width=1 in0_width=1 in10_width=1
in11_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 in16_width=1 in17_width=1 in18_width=1
in19_width=1 in1_width=1 in20_width=1 in21_width=1
in22_width=1 in23_width=1 in24_width=1 in25_width=1
in26_width=1 in27_width=1 in28_width=1 in29_width=1
in2_width=1 in30_width=1 in31_width=1 in3_width=1
in4_width=1 in5_width=1 in6_width=1 in7_width=1
in8_width=1 in9_width=1 iptotal=1 num_ports=1
x_ipcorerevision=1 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=xlconcat
x_ipproduct=Vivado 2018.2.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
xpm_memory_base/1
x_ipversion=2.1 addr_width_a=5 addr_width_b=5 auto_sleep_time=0
byte_write_width_a=167 byte_write_width_b=167 clocking_mode=0 core_container=NA
ecc_mode=0 iptotal=14 max_num_char=0 memory_optimization=true
memory_primitive=1 memory_size=5344 memory_type=1 message_control=0
num_char_loc=0 p_ecc_mode=no_ecc p_enable_byte_write_a=0 p_enable_byte_write_b=0
p_max_depth_data=32 p_memory_opt=yes p_memory_primitive=distributed p_min_width_data=167
p_min_width_data_a=167 p_min_width_data_b=167 p_min_width_data_ecc=167 p_min_width_data_ldw=4
p_min_width_data_shft=167 p_num_cols_write_a=1 p_num_cols_write_b=1 p_num_rows_read_a=1
p_num_rows_read_b=1 p_num_rows_write_a=1 p_num_rows_write_b=1 p_sdp_write_mode=yes
p_width_addr_lsb_read_a=0 p_width_addr_lsb_read_b=0 p_width_addr_lsb_write_a=0 p_width_addr_lsb_write_b=0
p_width_addr_read_a=5 p_width_addr_read_b=5 p_width_addr_write_a=5 p_width_addr_write_b=5
p_width_col_write_a=167 p_width_col_write_b=167 read_data_width_a=167 read_data_width_b=167
read_latency_a=2 read_latency_b=1 read_reset_value_a=0 read_reset_value_b=0
use_embedded_constraint=0 use_mem_init=0 version=0 wakeup_time=0
write_data_width_a=167 write_data_width_b=167 write_mode_a=1 write_mode_b=1
xpm_memory_sdpram/1
write_mode_b=1 addr_width_a=5 addr_width_b=5 auto_sleep_time=0
byte_write_width_a=167 clocking_mode=0 core_container=NA ecc_mode=0
iptotal=14 memory_optimization=true memory_primitive=1 memory_size=5344
message_control=0 p_clocking_mode=0 p_ecc_mode=0 p_memory_optimization=1
p_memory_primitive=1 p_wakeup_time=0 p_write_mode_b=1 read_data_width_b=167
read_latency_b=1 read_reset_value_b=0 use_embedded_constraint=0 use_mem_init=0
wakeup_time=0 write_data_width_a=167 write_mode_b=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 reqp-1709=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
lutar-1=2 pdrc-190=12 reqp-1959=16 timing-9=1
xdcb-5=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.024305 clocks=0.038068
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.064682 die=xc7a35ticsg324-1L dsp_output_toggle=12.500000 dynamic=0.795302
effective_thetaja=4.8 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.266683 input_toggle=12.500000
junction_temp=29.1 (C) logic=0.017195 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.194471 netlist_net_matched=NA
off-chip_power=0.505912 on-chip_power=0.859984 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=csg324 pct_clock_constrained=13.000000 pct_inputs_defined=2
phaser=0.111052 platform=nt64 pll=0.116367 process=typical
ram_enable=50.000000 ram_write=50.000000 read_saif=False set/reset_probability=0.000000
signal_rate=False signals=0.023378 simulation_file=None speedgrade=-1L
static_prob=False temp_grade=industrial thetajb=6.8 (C/W) thetasa=4.6 (C/W)
toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=4.8 user_junc_temp=29.1 (C)
user_thetajb=6.8 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.001600 vccadc_static_current=0.018000
vccadc_total_current=0.019600 vccadc_voltage=1.800000 vccaux_dynamic_current=0.272390 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.011454
vccaux_total_current=0.283844 vccaux_voltage=1.800000 vccbram_dynamic_current=0.001856 vccbram_static_current=0.000342
vccbram_total_current=0.002197 vccbram_voltage=0.950000 vccint_dynamic_current=0.143098 vccint_static_current=0.007042
vccint_total_current=0.150140 vccint_voltage=0.950000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.491977 vcco135_static_current=0.001000
vcco135_total_current=0.492977 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.001866 vcco33_static_current=0.001000
vcco33_total_current=0.002866 vcco33_voltage=3.300000 version=2018.2.1 xadc=0.003782

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=5 bufgctrl_util_percentage=15.63
bufhce_available=72 bufhce_fixed=0 bufhce_used=1 bufhce_util_percentage=1.39
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=1 mmcme2_adv_used=2 mmcme2_adv_util_percentage=40.00
plle2_adv_available=5 plle2_adv_fixed=1 plle2_adv_used=1 plle2_adv_util_percentage=20.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=1
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=1 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=18 block_ram_tile_util_percentage=36.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=18 ramb36_fifo_util_percentage=36.00
ramb36e1_only_used=18
primitives
and2b1l_functional_category=Others and2b1l_used=4 bscane2_functional_category=Others bscane2_used=1
bufg_functional_category=Clock bufg_used=5 bufh_functional_category=Clock bufh_used=1
carry4_functional_category=CarryLogic carry4_used=174 fdce_functional_category=Flop & Latch fdce_used=242
fdpe_functional_category=Flop & Latch fdpe_used=53 fdre_functional_category=Flop & Latch fdre_used=10126
fdse_functional_category=Flop & Latch fdse_used=414 ibuf_functional_category=IO ibuf_intermdisable_functional_category=IO
ibuf_intermdisable_used=16 ibuf_used=19 ibufds_intermdisable_int_functional_category=IO ibufds_intermdisable_int_used=4
idelayctrl_functional_category=IO idelayctrl_used=1 idelaye2_functional_category=IO idelaye2_used=16
in_fifo_functional_category=IO in_fifo_used=2 inv_functional_category=LUT inv_used=3
iserdese2_functional_category=IO iserdese2_used=16 lut1_functional_category=LUT lut1_used=467
lut2_functional_category=LUT lut2_used=919 lut3_functional_category=LUT lut3_used=2625
lut4_functional_category=LUT lut4_used=1697 lut5_functional_category=LUT lut5_used=2468
lut6_functional_category=LUT lut6_used=2524 mmcme2_adv_functional_category=Clock mmcme2_adv_used=2
muxf7_functional_category=MuxFx muxf7_used=114 obuf_functional_category=IO obuf_used=25
obufds_functional_category=IO obufds_used=2 obuft_functional_category=IO obuft_used=30
obuftds_functional_category=IO obuftds_used=4 oddr_functional_category=IO oddr_used=5
oserdese2_functional_category=IO oserdese2_used=43 out_fifo_functional_category=IO out_fifo_used=4
phaser_in_phy_functional_category=IO phaser_in_phy_used=2 phaser_out_phy_functional_category=IO phaser_out_phy_used=4
phaser_ref_functional_category=IO phaser_ref_used=1 phy_control_functional_category=IO phy_control_used=1
plle2_adv_functional_category=Clock plle2_adv_used=1 ramb36e1_functional_category=Block Memory ramb36e1_used=18
ramd32_functional_category=Distributed Memory ramd32_used=2062 rams32_functional_category=Distributed Memory rams32_used=644
srl16e_functional_category=Distributed Memory srl16e_used=209 srlc16e_functional_category=Distributed Memory srlc16e_used=7
srlc32e_functional_category=Distributed Memory srlc32e_used=272 xadc_functional_category=Others xadc_used=1
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=114 f7_muxes_util_percentage=0.70
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=1354 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=8665 lut_as_logic_util_percentage=41.66 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=1769 lut_as_memory_util_percentage=18.43 lut_as_shift_register_fixed=0 lut_as_shift_register_used=415
register_as_and_or_available=41600 register_as_and_or_fixed=0 register_as_and_or_used=4 register_as_and_or_util_percentage=<0.01
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=10835 register_as_flip_flop_util_percentage=26.05
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=10434 slice_luts_util_percentage=50.16
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=10839 slice_registers_util_percentage=26.06
fully_used_lut_ff_pairs_fixed=26.06 fully_used_lut_ff_pairs_used=1422 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=1354
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=8665 lut_as_logic_util_percentage=41.66
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=1769 lut_as_memory_util_percentage=18.43
lut_as_shift_register_fixed=0 lut_as_shift_register_used=415 lut_ff_pairs_with_one_unused_flip_flop_fixed=415 lut_ff_pairs_with_one_unused_flip_flop_used=3053
lut_ff_pairs_with_one_unused_lut_output_fixed=3053 lut_ff_pairs_with_one_unused_lut_output_used=3053 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=4937 lut_flip_flop_pairs_util_percentage=23.74 slice_available=8150 slice_fixed=0
slice_used=3654 slice_util_percentage=44.83 slicel_fixed=0 slicel_used=2486
slicem_fixed=0 slicem_used=1168 unique_control_sets_used=461 using_o5_and_o6_fixed=461
using_o5_and_o6_used=73 using_o5_output_only_fixed=73 using_o5_output_only_used=24 using_o6_output_only_fixed=24
using_o6_output_only_used=318
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=1 bscane2_util_percentage=25.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=1 xadc_util_percentage=100.00

router
usage
actual_expansions=11903288 bogomips=0 bram18=0 bram36=18
bufg=0 bufr=0 congestion_level=0 ctrls=461
dsp=0 effort=2 estimated_expansions=16015734 ff=10839
global_clocks=5 high_fanout_nets=6 iob=68 lut=11507
movable_instances=26236 nets=38811 pins=160784 pll=1
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35ticsg324-1L
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=design_1_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:29s hls_ip=0 memory_gain=467.895MB memory_peak=914.391MB