Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.


software_version_and_target_device
betaFALSE build_version2086221
date_generatedTue Feb 26 16:18:13 2019 os_platformWIN64
product_versionVivado v2017.4 (64-bit) project_id10b795e6d3b44957819056bbf29e08db
project_iteration2 random_ida91cfa5951b1516890b4fa4e8ef059db
registration_id176233316_1777497009_210621211_364 route_designTRUE
target_devicexc7a200t target_familyartix7
target_packagesbg484 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-6700 CPU @ 3.40GHz cpu_speed3408 MHz
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
system_ram17.000 GB total_processors1

vivado_usage
gui_handlers
addrepositoryinfodialog_ok=1 basedialog_cancel=1 basedialog_ok=43 cmdmsgdialog_ok=1
constraintschooserpanel_create_file=1 coretreetablepanel_core_tree_table=17 createconstraintsfilepanel_file_name=1 filesetpanel_file_set_panel_tree=55
flownavigatortreepanel_flow_navigator_tree=27 gettingstartedview_create_new_project=1 hfolderchooserhelpers_up_one_level=6 msgtreepanel_message_view_tree=13
msgview_critical_warnings=1 msgview_error_messages=2 pacommandnames_add_sources=1 pacommandnames_auto_connect_target=1
pacommandnames_auto_update_hier=3 partchooser_boards=2 paviews_code=1 paviews_ip_catalog=2
programdebugtab_open_target=1 programdebugtab_program_device=4 programfpgadialog_program=4 projectnamechooser_choose_project_location=2
projectnamechooser_project_name=2 rdicommands_delete=2 rdicommands_line_comment=8 removesourcesdialog_also_delete=1
settingsdialog_project_tree=2 settingsprojectiprepositorypage_add_repository=1 simpleoutputproductdialog_generate_output_products_immediately=17 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1
srcchooserpanel_add_or_create_source_file=1 srcchooserpanel_make_local_copy_of_these_files_into=1 srcmenu_ip_documentation=3 srcmenu_ip_hierarchy=2
srcmenu_refresh_hierarchy=1 taskbanner_close=1
java_command_handlers
addsources=1 autoconnecttarget=1 coreview=3 customizecore=6
editdelete=2 launchprogramfpga=4 newproject=1 openhardwaremanager=1
recustomizecore=13 runbitgen=14 savefileproxyhandler=1 showview=8
toolssettings=1
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=16 export_simulation_ies=16
export_simulation_modelsim=16 export_simulation_questa=16 export_simulation_riviera=16 export_simulation_vcs=16
export_simulation_xsim=16 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=4 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=3 bufio=1 bufr=1 carry4=18
fdce=13 fdpe=25 fdre=574 fdse=27
gnd=43 ibuf=4 ibufds=4 idelayctrl=1
idelaye2=3 iserdese2=6 lut1=25 lut2=82
lut3=104 lut4=104 lut5=117 lut6=242
mmcme2_adv=1 muxf7=19 muxf8=8 obuf=1
obufds=4 obuft=2 oserdese2=8 plle2_adv=2
ramd32=36 rams32=12 vcc=52
pre_unisim_transformation
bufg=3 bufio=1 bufr=1 carry4=18
fdce=13 fdpe=25 fdre=574 fdse=27
gnd=43 ibuf=2 ibufds=4 idelayctrl=1
idelaye2=3 iobuf=2 iserdese2=6 lut1=25
lut2=82 lut3=104 lut4=104 lut5=117
lut6=242 mmcme2_adv=1 muxf7=19 muxf8=8
obuf=1 obufds=4 oserdese2=8 plle2_adv=2
ram32m=6 vcc=52

ip_statistics
clk_wiz_v5_4_3_0/1
clkin1_period=8.000 clkin2_period=10.0 clock_mgr_type=NA component_name=clk_wiz_125M_200M
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=PLL
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
ckbf-1=1 timing-18=3 timing-2=1 timing-4=2
timing-9=1 xdcb-5=2 xdcc-1=1 xdcc-7=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") clocks=0.015856 confidence_level_clock_activity=High
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Medium
confidence_level_overall=Medium customer=TBD customer_class=TBD devstatic=0.123930
die=xc7a200tsbg484-1 dsp_output_toggle=12.500000 dynamic=0.404948 effective_thetaja=3.3
enable_probability=0.990000 family=artix7 ff_toggle=12.500000 flow_state=routed
heatsink=medium (Medium Profile) i/o=0.033935 input_toggle=12.500000 junction_temp=26.8 (C)
logic=0.001400 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 mmcm=0.112522 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=0.528879 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=sbg484 pct_clock_constrained=2.000000 pct_inputs_defined=25 platform=nt64
pll=0.244589 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.001038
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=5.0 (C/W) thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=3.3 user_junc_temp=26.8 (C) user_thetajb=5.0 (C/W) user_thetasa=4.6 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.200855 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.030670 vccaux_total_current=0.231525 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000000 vccbram_static_current=0.000765 vccbram_total_current=0.000765 vccbram_voltage=1.000000
vccint_dynamic_current=0.043410 vccint_static_current=0.031959 vccint_total_current=0.075368 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.000000 vcco33_static_current=0.000000 vcco33_total_current=0.000000 vcco33_voltage=3.300000
version=2017.4

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=5 bufgctrl_util_percentage=15.63
bufhce_available=120 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=40 bufio_fixed=0 bufio_only_fixed=0 bufio_only_used=1
bufio_used=1 bufio_util_percentage=2.50 bufmrce_available=20 bufmrce_fixed=0
bufmrce_used=0 bufmrce_util_percentage=0.00 bufr_available=40 bufr_fixed=0
bufr_used=1 bufr_util_percentage=2.50 mmcme2_adv_available=10 mmcme2_adv_fixed=0
mmcme2_adv_used=1 mmcme2_adv_util_percentage=10.00 plle2_adv_available=10 plle2_adv_fixed=0
plle2_adv_used=2 plle2_adv_util_percentage=20.00
dsp
dsps_available=740 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=1 lvcmos15=0
lvcmos18=0 lvcmos25=1 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=1
memory
block_ram_tile_available=365 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=730 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=365 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=5 bufio_functional_category=Clock bufio_used=1
bufr_functional_category=Clock bufr_used=1 carry4_functional_category=CarryLogic carry4_used=18
fdce_functional_category=Flop & Latch fdce_used=13 fdpe_functional_category=Flop & Latch fdpe_used=25
fdre_functional_category=Flop & Latch fdre_used=574 fdse_functional_category=Flop & Latch fdse_used=27
ibuf_functional_category=IO ibuf_used=4 ibufds_functional_category=IO ibufds_used=4
idelayctrl_functional_category=IO idelayctrl_used=1 idelaye2_functional_category=IO idelaye2_used=3
iserdese2_functional_category=IO iserdese2_used=6 lut1_functional_category=LUT lut1_used=19
lut2_functional_category=LUT lut2_used=82 lut3_functional_category=LUT lut3_used=104
lut4_functional_category=LUT lut4_used=107 lut5_functional_category=LUT lut5_used=114
lut6_functional_category=LUT lut6_used=242 mmcme2_adv_functional_category=Clock mmcme2_adv_used=1
muxf7_functional_category=MuxFx muxf7_used=19 muxf8_functional_category=MuxFx muxf8_used=8
obuf_functional_category=IO obuf_used=1 obufds_functional_category=IO obufds_used=4
obuft_functional_category=IO obuft_used=2 oserdese2_functional_category=IO oserdese2_used=8
plle2_adv_functional_category=Clock plle2_adv_used=2 ramd32_functional_category=Distributed Memory ramd32_used=36
rams32_functional_category=Distributed Memory rams32_used=12
slice_logic
f7_muxes_available=66900 f7_muxes_fixed=0 f7_muxes_used=19 f7_muxes_util_percentage=0.03
f8_muxes_available=33450 f8_muxes_fixed=0 f8_muxes_used=8 f8_muxes_util_percentage=0.02
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24 lut_as_logic_available=133800 lut_as_logic_fixed=0
lut_as_logic_used=535 lut_as_logic_util_percentage=0.40 lut_as_memory_available=46200 lut_as_memory_fixed=0
lut_as_memory_used=24 lut_as_memory_util_percentage=0.05 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_as_flip_flop_available=267600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=639 register_as_flip_flop_util_percentage=0.24
register_as_latch_available=267600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=133800 slice_luts_fixed=0 slice_luts_used=559 slice_luts_util_percentage=0.42
slice_registers_available=267600 slice_registers_fixed=0 slice_registers_used=639 slice_registers_util_percentage=0.24
fully_used_lut_ff_pairs_fixed=0.24 fully_used_lut_ff_pairs_used=84 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24
lut_as_logic_available=133800 lut_as_logic_fixed=0 lut_as_logic_used=535 lut_as_logic_util_percentage=0.40
lut_as_memory_available=46200 lut_as_memory_fixed=0 lut_as_memory_used=24 lut_as_memory_util_percentage=0.05
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=148
lut_ff_pairs_with_one_unused_lut_output_fixed=148 lut_ff_pairs_with_one_unused_lut_output_used=201 lut_flip_flop_pairs_available=133800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=293 lut_flip_flop_pairs_util_percentage=0.22 slice_available=33450 slice_fixed=0
slice_used=221 slice_util_percentage=0.66 slicel_fixed=0 slicel_used=158
slicem_fixed=0 slicem_used=63 unique_control_sets_used=40 using_o5_and_o6_fixed=40
using_o5_and_o6_used=24 using_o5_output_only_fixed=24 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=0
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=1809510 bogomips=0 bram18=0 bram36=0
bufg=0 bufr=1 congestion_level=0 ctrls=40
dsp=0 effort=2 estimated_expansions=598026 ff=639
global_clocks=5 high_fanout_nets=0 iob=21 lut=622
movable_instances=1534 nets=1672 pins=8629 pll=2
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a200tsbg484-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=hdmi_pass_top -verilog_define=default::[not_specified]
usage
elapsed=00:00:32s hls_ip=0 memory_gain=521.063MB memory_peak=887.047MB